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SG1010 Data Sheet
Revision Information: Copy Number:
4 000
StarGen, Inc., 225 Cedar Hill Street, Suite 22, Marlborough, MA 01752 www.stargen.com
October 2003
StarGen, Inc. believes the information in this publication is correct; however, the information is subject to change without notice. StarGen, Inc. does not claim that the use of its products in the manner described in this publication will not infringe on any existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. (c)StarGen, Inc. 2003. All rights reserved. Printed in U.S.A. StarGen, StarProtocol, StarFabric, and the STARGEN logo are trademarks of StarGen, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Table of Contents
Introduction Features
2.1 2.2 2.3 2.4 2.5 Scalability and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Reliability, Availability, Serviceability features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
StarFabric Features
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Scalability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Compenent Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Routing Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Traffic Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Fault Tolerant Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Bandwidth Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Usage Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Specifications
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Pin List By Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Package Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Electrical Specifications
5.1 5.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
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5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6
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Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Serial ROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Global PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 StarFabric Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Diagnostic Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Asynchronous and Static Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Contact Information
6.1 Headquarters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
2
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1
Introduction
The StarGen SG1010 StarSwitch facilitates the design of high-performance and reliable StarFabric based switching systems. System designers can develop high performance systems that deliver voice, video, and data. A single-chip solution, the SG1010 offers six 2.5Gbps full duplex serial links, which deliver 30Gbps of aggregate, non-blocking, full duplex switching capacity. Along with its high performance, the SG1010 can handle content-rich traffic through its extensive functionality and Quality of Service (QOS) support. The SG1010 supports 4 classes of service along with three routing methods providing added flexibility. The SG1010 is designed to work with other StarFabric devices and supports bridge products that employ protocols such as PCI and H.110. System designers can build system architectures that easily combine control, voice, cell and packet data. The SG1010 allows PCI based designs to be easily migrated to StarFabric, yet maintain their investments in software and applications. The SG1010 supports two addressing models - a StarFabric address model and a PCI address model. In the StarFabric address model, the SG1010 switches path-routed and multicast frames. To support the PCI address model, the SG1010 appears as a PCI-to-PCI bridge to PCI configuration software. The SG1010 includes a PCI-compliant type1 header for 100% compatibility with existing PCI BIOS, drivers, application SW, and operating systems. Designers don't have to deal with significant physical interface issues, which minimizes time-to-market. The SG1010 utilizes 622Mbps low voltage differential signaling (LVDS), a technology that is widely applied and thoroughly understood by industry professionals. Four transmit and receive differential pairs create a single 2.5Gbps full duplex link with 5Gbps of total bandwidth. StarFabric designs can span from chip-tochip to room area networks. Inexpensive twisted pair copper cable can yield distances greater than 10 meters. The SG1010 allows system designers to cost effectively engineer highly reliable and available systems. SG1010 system designs can include redundant data paths, so if a particular path fails, traffic can be rerouted over an alternate path. The SG1010 supports detection and notification of link status changes, as well as Hot-pluggable links. Path notification messages alerts operations personnel to replace faulty components and through hot swap, the offending boards can be replaced without affecting the rest of the
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Introduction
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system. The 2.5 Gbps links also tolerate failure of up to three of the four differential pairs in a link. The re-striping of data is done automatically in silicon when differential pairs fail. By combining the SG1010 with other StarFabric Devices, new multi-protocol, highly reliable, high performance systems can be acheived. The SG1010 offers a comprehensive solution, which includes silicon, software, and platforms to help achieve faster time-to- market.
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Introduction
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2
Features
2.1 Scalability and Performance
* * * *
6 fabric links, 2.5 Gbps, full duplex 30 Gbps switching capacity Design limits head-of-line blocking Credit-based flow control
2.2 Compatibility
* * *
Support for routing methods including PC compatible address routing Flexible Addressing Capability Physical layer interface is compliant with the IEEE 1596.3 and TIA/EIA-644 LowVoltage Differential Signaling (LVDS) standards.
2.3 Quality of Service
* * * * *
Specific credits for next-turn and class-of-service Separate buffering for Asynchronous, Isochronous, Multicast, and High Priority traffic classes. Path routing Multicast routing Dynamic bandwidth reservation protocol
2.4 Reliability, Availability, Serviceability features
* * *
Link-by-link CRC checking on all traffic Redundant path routing capability Hot-pluggable links
2.5 Additional features
*
IEEE standard 1149.1 JTAG interface
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Features
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Additional features * *
Eight general-purpose I/O pins with accessible registers LED indicators for each differential pair
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Features
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3
StarFabric Features
3.1 Scalability
Bridge Bridge Bridge
Switch
Bridge Bridge Bridge
The SG1010 switch has 30Gbps of switching capacity. When cascaded, the device enables systems to scale to gigabytes per second of capacity. The initial physical layer implemented provides 2.5 Gbps full-duplex bandwidth per link. Two links can be aggregated to create a `fat pipe' with double the bandwidth. The links are well suited for chip-to-chip, backplane, and rack-to-rack interconnect. Using standard category 5 unshielded copper cables the links can extend to over 10 meters in length enabling the creation of room scale equipment.
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StarFabric Features
3-5
Compenent Types
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3.2 Compenent Types
The two component types in StarFabric are edge nodes and switches. Swithes forward traffic through the StarFabric. Edge nodes provide the connection between the fabric and other protocols or devices. Bridges are edge nodes that translate other protocols (e.g., PCI, H.110) into serial StarFabric traffic. An edge node is further classified into either a root or a leaf. The root initiates fabric resets and enumeration.
3.3 Routing Methods
* *
Address Routing - - Provides full compatibility with standards like PCI, Path and Multicast routing Provides Quality of service, reliability, and high availability Path and Multicast routing
3.4 Traffic Classes
StarFabric supports 7 traffic classes. The initial parts support 4 traffic classes.
* * * *
Asynchronous / address routed class Isochronous Class Multicast Class High Priority Class
3.5 Fault Tolerant Strategies
*
Parallel Fabrics - A second fabric provides redundancy. Redundant switches are used so that any switch may fail, yet end nodes remain connected. If a particular path fails, packets can be re-routed by silicon or software over the remaining functional paths. Automatic re stripping of data over functioning differential pairs in a link when one to three pairs fail.
*
Fragile links -
3.6 Flow Control
Line credits manage flow control. Line credits are counters used to track available buffer storage between link partners. Each transmission point in the fabric has buffers for each class of traffic for each outgoing port. Traffic is sent only when the source has line credits for the output buffer on the next node for an entire frame. A switch is nonblocking because edge node congestion does not impact traffic flow to any other edge node or even to the same edge node in a different class of service. Line credits are used when a node sends a frame and restored when the node's link partner forwards the frame.
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Bandwidth Reservation
3.7 Bandwidth Reservation
Isochronous and multicast transmissions can use bandwidth reservation to allocate anticipated bandwidth requirements prior to starting data transfer. Bandwidth reservation is fully distributed and is initiated at the origin of the traffic.
3.8 Usage Models
Current StarFabric components support 3 usage models, PCI legacy, Fabric-native, and mixed legacy / Fabric-native. PCI legacy enables use of existing PCI drivers and initialization software with no modification. the interconnect looks like a collection of PCIto-PCI bridges. This usage model amounts to a plug-and-play mode that extends the capabilities of existing systems. The Fabric-native usage unleashes some of the StarFabric's advanced features such as path routing, class of service, bandwidth selection, redundancy for fail-over path routing, and channels. Fabric-native use also provides the isolation and mechanisms required for inter-processor communication. This enables distributed computing applications. It is possible to use a mixture of legacy and fabric-native capabilities. Developers can start with legacy and add enhanced fabric- native capability over time. To use advanced features, some degree of software investment is necessary. StarGen provides software tools to take advantage of StarFabric's advanced features. Sample software includes enumeration and routing, bandwidth reservation, as well as routines for optimizing performance, API integration layers, BIOS/initial setup, and generating statistics. StarGen supplies tools and utilites for ROM programming, fabric access tools, and Fabric topology viewers.
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StarFabric Features
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4
Specifications
4.1 Block Diagram
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Package Diagram
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4.2 Package Diagram
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15
16 17
18 19
20
Ground BGA signal pin I/O power = 3.3V Core power = 1.5V CDR Power=1.5V
A B C D E F G H J K L M N P R T U V W Y
vSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Vss
VSS
VSS
VSS
Vss
VSS
VSS
VSS
Figure 4-1 Top View Package Diagram
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Specifications
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Pinout Diagram
4.3 Pinout Diagram
TX0P[3:0]
GPIO PINS
GPIO [7:0]
TX0N[3:0] TX1P[3:0] TX1N[3:0] TX2P[3:0] TX2N[3:0] TX3P[3:0] TX3N[3:0] TX4P[3:0] TX4N[3:0] TX5P[3:0] TX5N[3:0] RX0P[3:0] RX0N[3:0] RX1P[3:0] RX1N[3:0]
SR_DO SR_DI
SERIAL ROM INTERFACE
SR_CK SR_CS_L
VDDG VSSG
RX2P[3:0] RX2N[3:0] RX3P[3:0]
GLOBAL PLL AND RESET
TSTCLKG PLLCLKGO
RX3N[3:0] RX4P[3:0] RX4N[3:0] RX5P[3:0] RX5N[3:0] CTAP0[3:0] CTAP1[3:0]
LINK INTERFACE
NRST_L
TESTMODE [4:0]
Test Mode Control
SG1010 SG2010 (272 Pins) (272 Pins)
CTAP2[3:0] CTAP3[3:0] CTAP4[3:0] CTAP5[3:0] RESLO RESHI REF14
DIAG_EN
AD[3:0] AD[7:4]
REF10 REFCLKL VDDA VSSA
Diagnostic Port*
RDY_L AS_L WR_L RD_L
TCK TDI
LED0_L[3:0] LED1_L[3:0] LED2_L[1:0]
JTAG
TDO TMS TRST_L
LED2_L[3:2] LED3_L[3:0] LED4_L[3:0] LED5_L[3] LED5_L[2] LED5_L[1] LED5_L[0]
Link LED Indicators *
*Shared Pins with Diagnostic and Link Led
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Specifications
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Pin List By Location
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4.4 Pin List By Location
Table 4-1 Pin by Location
Pin Signal Name Type
B1 C2 D2 D3 E4 E3 D1 C1 E2 E1 F3 G4 F2 F1 G3 G2 G1 H3 H2 H1 J4 J3 J2 J1 K2 K3 K1 L1 L2 L3 M1 M2 M3 M4 N1 N2
tx1p[0] tx1n[0] tx1p[1] tx1n[1] tx1p[2] tx1n[2] tx1p[3] tx1n[3] tx0p[0] tx0n[0] tx0p[1] tx0n[1] tx0p[2] tx0n[2] tx0p[3] tx0n[3] tx5p[0] tx5n[0] tx5p[1] tx5n[1] tx5p[2] tx5n[2] tx5p[3] tx5n[3] reserved[0] reserved[1] reserved[2] reserved[3] reserved[4] reserved[5] reserved[6] reserved[7] reserved[8] reserved[9] reserved[10] reserved[11]
O O O O O O O O O O O O O O O O O O O O O O O O IO IO IO IO IO IO IO IO IO IO IO IO
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Table 4-1 Pin by Location
Pin Signal Name
Pin List By Location
Type
N3 P1 P2 R1 P3 R2 T1 P4 R3 T2 U1 T3 U2 V1 U3 V2 W1 V3 W2 Y1 W3 Y2 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 V7 W7 Y7 V8 W8
reserved[12] reserved[13] reserved[14] reserved[15] reserved[16] reserved[17] reserved[18] diag_en testmode[4] tck trst_l tms tdo tdi scan_ena spare scan_out[0] scan_out[1] scan_out[2] scan_out[3] scan_out[4] scan_out[5] scan_out[6] scan_out[7] testmode[3] testmode[2] testmode[1] testmode[0] sr_cs_l sr_ck sr_di sr_do gpio[7] gpio[6] gpio[5] gpio[4] gpio[3] gpio[2]
IO IO IO IO IO IO IO I I I I I O I I I IO IO IO IO IO IO IO IO I I I I IO IO IO I IO IO IO IO IO IO
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Pin List By Location
Table 4-1 Pin by Location
Pin Signal Name Type
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Y8 U9 V9 W9 Y9 W10 V10 Y10 Y11 W11 V11 Y12 W12 V12 U12 Y13 Y14 W14 Y15 V14 W15 Y16 U14 V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 Y20 W20 V19
gpio[1] gpio[0] nrst_l tstclkg pllclkgo led5_l[3] led5_l[2] led5_l[1] led5_l[0] led4_l[3] led4_l[2] led4_l[1] led4_l[0] led3_l[3] led3_l[2] led3_l[1] led3_l[0] led2_l[3] led2_l[2] led2_l[1] led2_l[0] led1_l[3] led1_l[2] led1_l[1] led1_l[0] led0_l[3] led0_l[2] led0_l[1] led0_l[0] tstshftld ecsel etoggle exdnup tstphase resettx loopbken testrst bypassl
IO IO I I O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I I I I I I I I I
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Table 4-1 Pin by Location
Pin Signal Name
Pin List By Location
Type
U19 U18 T17 V20 U20 T18 T19 T20 R18 P17 R19 R20 P18 P19 P20 N18 N19 N20 M18 M19 M20 L19 L18 K19 K18 J19 J18 J17 H20 H19 H18 G20 G18 F19 E20 G17 F18 E18
tstclkl refclkl ctap5[0] rx5p[0] rx5n[0] rx5p[1] rx5n[1] ctap5[1] rx5p[2] rx5n[2] ctap5[2] ctap5[3] rx5p[3] rx5n[3] ctap0[0] rx0p[0] rx0n[0] ctap0[1] rx0p[1] rx0n[1] rx0p[2] rx0n[2] ctap0[2] rx0p[3] rx0n[3] ctap0[3] rx1p[0] rx1n[0] ctap1[0] rx1p[1] rx1n[1] ctap1[1] rx1p[2] rx1n[2] ctap1[2] rx1p[3] rx1n[3] ctap1[3]
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
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Pin List By Location
Table 4-1 Pin by Location
Pin Signal Name Type
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D19 C20 E17 D18 C19 B20 C18 B19 A20 A19 B18 B17 C17 D16 A18 A17 C16 B16 A16 C15 D14 B15 A15 C14 B14 A14 C13 B13 A13 D12 C12 B12 A12 B11 C11 A11 A10 B10
rx2p[0] rx2n[0] ctap2[0] rx2p[1] rx2n[1] ctap2[1] rx2p[2] rx2n[2] ctap2[2] rx2p[3] rx2n[3] ctap2[3] rx3p[0] rx3n[0] ctap3[0] rx3p[1] rx3n[1] ctap3[1] ctap3[2] rx3p[2] rx3n[2] rx3p[3] rx3n[3] ctap3[3] rx4p[0] rx4n[0] ctap4[0] rx4p[1] rx4n[1] ctap4[1] rx4p[2] rx4n[2] ctap4[2] rx4p[3] rx4n[3] ctap4[3] tx4p[0] tx4n[0]
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O
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Table 4-1 Pin by Location
Pin Signal Name Type
Power Pins
C10 C9 B9 A9 D9 C8 B8 A8 A7 B7 B6 C7 A6 A5 D7 C6 B5 A4 C5 B4 A3 B3 C4 B2 A2 C3
tx4p[1] tx4n[1] tx4p[2] tx4n[2] tx4p[3] tx4n[3] tx3p[0] tx3n[0] tx3p[1] tx3n[1] tx3p[2] tx3n[2] tx3p[3] tx3n[3] tx2p[0] tx2n[0] tx2p[1] tx2n[1] tx2p[2] tx2n[2] tx2p[3] tx2n[3] reslo reshi ref14 ref10
O O O O O O O O O O O O O O O O O O O O O O I I I I
4.5 Power Pins
Table 4-2 Power Pins
Description Pins
Ground Vdd 3.3V Vdd 1.5V Analog 1.5V Vssa
A1,D4,D8,D13,D17,H4,H17,J9,J10,J11,J12,K9,K10,K11,K12,L9,L11,L12 ,M9,M10,M11,M12,N4,N17,U4,U8,U13,U17 D11,F4,F17,R4,R17,U10,D10,T4,U7 D6,D15,K4,L17,U6,U15,D5,L4,M17,U11 L20,G19,K17,E19,W13 V13,K20,J20,D20,F20
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4.6 Pin Descriptions
Table 4-3 Pin Descriptions
Pin Description
SR_DO SR_DI SR_CK SR_CS_L VDDG VSSG TSTCLKG PLLCLKGO NRST_L TX0P[3:0] TX0N[3:0] TX1P[3:0] TX1N[3:0] TX2P[3:0] TX2N[3:0] TX3P[3:0] TX3N[3:0] TX4P[3:0] TX4N[3:0] TX5P[3:0] TX5N[3:0] RX0P[3:0] RX0N[3:0] RX1P[3:0] RX1N[3:0] RX2P[3:0] RX2N[3:0] RX3P[3:0] RX3N[3:0] RX4P[3:0] RX4N[3:0] RX5P[3:0] RX5N[3:0] REFCLKL
SROM data out. Receives read data from the Serial Rom. SROM data in. The SG1010 drives the SROM command, address, and write data on this signal SROM clock input. SROM chip select. The SG1010 drives this signal low at the beginning of an SROM operation; high at the end of the operation VDD for 112.5MHz phase-locked loop (PLL) VSS for 112.5MHz PLL Bypass clock for 112.5 MHz PLL. Bypass mode is selected through TESTMODE [4:0] pins 112.5MHz PLL output (used for test) Chip reset pin Link 0 LVDS transmit positive Link 0 LVDS transmit negative Link 1 LVDS transmit positive Link 1 LVDS transmit negative Link 2 LVDS transmit positive Link 2 LVDS transmit negative Link 3 LVDS transmit positive Link 3 LVDS transmit negative Link 4 LVDS transmit positive Link 4 LVDS transmit negative Link 5 LVDS transmit positive Link 5 LVDS transmit negative Link 0 LVDS receive positive Link O LVDS receive negative Link 1 LVDS receive positive Link 1 LVDS receive negative Link 2 LVDS receive positive Link 2 LVDS receive negative Link 3 LVDS receive positive Link 3 LVDS receive negative Link 4 LVDS receive positive Link 4 LVDS receive negative Link 5 LVDS receive positive Link 5 LVDS receive negative Reference clock for CDR PLL
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Specifications
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Table 4-3 Pin Descriptions
Pin Description
Pin Descriptions
CTAP0[3:0] CTAP1[3:0] CTAP2[3:0] CTAP3[3:0] CTAP4[3:0] CTAP5[3:0] RESLO RESHI REF14 REF10 VDDA VSSA TSTCLKL BYPASSL RESETTX TESTRST TSTSHFTLD ECSEL ETOGGLE EXDNUP TSTPHASE LOOPBKEN TESTMODE[4:0] DIAG_EN LED0_L[3:0] LED1_L[3:0] LED2_L[3:0] LED3_L[3:0] LED4_L[3:0] LED5_L[3:0] TCK TDI TDO TMS TRST_L SCAN_ENA SCAN_OUT[7:0]
Link 5 LVDS center taps for external reference voltages Link 5 LVDS center taps for external reference voltages Link 5 LVDS center taps for external reference voltages Link 5 LVDS center taps for external reference voltages Link 5 LVDS center taps for external reference voltages Link 5 LVDS center taps for external reference voltages LVDS 100OHM reference low- connects to RESHI through 100OHM 1% resistor LVDS 100OHM reference high- connects to RESLO through 100 OHM 1% resistor LVDS 1.4V reference LVDS 1.0V reference Analog VDD for CDR PLL Analog VSS for CDR PLL Manufacturing Test Pin Manufacturing Test Pin Manufacturing Test Pin Manufacturing Test Pin Manufacturing Test Pin Manufacturing Test Pin Manufacturing Test Pin Manufacturing Test Pin Manufacturing Test Pin Manufacturing Test Pin Enables SG1010 functional/test Diagnostic Port Enable Transmit state LEDs for link0 Transmit state LEDs for link1 Transmit state LEDs for link2 Link 3 state LEDs Link 4 state LEDs Link 5 state LEDs JTAG clock JTAG data in JTAG data out JTAG mode select JTAG reset Scan enable input Scan chain outputs
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Specifications
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Package Specification
Table 4-3 Pin Descriptions
Pin Description
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AD[7:0] RDY_L AS_L WR_L RD_L
Diagnostic port AD[7:0] Diagnostic Port Control Signal: Target Ready Diagnostic Port Control Signal: Address Strobe Diagnostic Port Control Signal: Write strobe Diagnostic Port Control Signal: read strobe
4.7 Package Specification
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Specifications
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5
Electrical Specifications
5.1 Absolute Maximum Ratings
Table 5-1 Absolute Maximum Ratings Junction Temperature Core Supply Voltage I/O Supply Voltage Storage Temperature Operating Temperature Power dissipation 0 to 125 degrees C 1.5V +/-5% 3.3V +/-5% -55 to 125 degrees C 0 to 70 degrees C 3W maximum
5.2 DC Specifications
Table 5-2 DC Specifications (non-LVDS signals)
Symbol Parameter Condition Min Max
Vih Vil Vipu Voh Vol Iin Iin-pme Cin
Input high voltage Input low voltage Input Pull-up voltage Output high voltage Output low voltage Input leakage current PME_L input leakage Pin capacitance
- - - Ioh = -500mA Iol = 1500mA 0 < Vin < Vio Vo < 3.6V Vcc off -
.5Vcc -0.5V .7Vcc .9Vcc - - - -
.5Vcc+.5V .3Vcc - - .1Vcc + 10 A -1 mA 10 pF
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5.3 Timing Specifications
5.3.1 Serial ROM Interface
Table 5-3 Serial ROM Interface AC Timing Specifications
Signal Symbol Parameter Min Max
SR_CLK SR_CS_L SR_CS_L SR_DO SR_DO SR_DI SR_DI
Tscyc Tscsl Tscssu Tsdosu Tsdoh Tsdivalb Tsdivala
Cycle time Minimum time low Setup to SR_CLK rising Setup to SR_CLK rising Hold from SR_CLK rising Valid before SR_CLK rising Valid from SR_CLK rising
510ns 56.5*Tscyc .5*Tscyc 30ns 30ns .5*Tscyc .5*Tscyc
- - - - - - -
5.3.2 Global PLL Timing
Table 5-4 Global PLL and Reset AC Timing Specifications
Signal Symbol Parameter Min Max
REFCLKL Fxtal REFCLKL Vrefptp REFCLKL REFCLKC NRST_L Trstv
Frequency Peak-to-peak voltage Slew rate Duty Cycle Minimum assertion time after power stable
62.208MHz 62.208MHz - 20ppm + 20ppm X V/ns 10 Y V/ns
5.3.3 StarFabric Interface Timing
Table 5-5 LVDS StarFabric Interface AC Timing Specifications
Signal Symbol Parameter Min Max
TXnP, TXnN TXnP, TXnN TXnP, TXnN TXnP, TXnN RXnP, RXnN RXnP, RXnN RXnP, RXnN RXnP, RXnN
Ttdpsk Ttppsk Ttdpr (2) Ttdpf (2) Trdpsk Trppsk Trdpr Trdpf
Differential skew Pair to pair skew Low to high time High to low time Differential skew Pair to pair skew Low to high time High to low time Maximum frequency 100ps 100ps
50ps 200ps 210ps 210ps 2ns
TXnP, TXnN, RXnP, RXnN Tdpfreq
(2) Test conditions: ZL=100O1%, Cpad=3.0pF, Cpadn=3.0pF
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Electrical Specifications
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Timing Specifications
5.3.4 Diagnostic Port Timing
Table 5-6 Diagnostic Port Read Operation Timing Diagram
tya tas AS_L WR_L tar RD_L tryl RDY_L trd AD[7:0] ADDR[3:0] tds DATA[7:0] tdh tryh tyr tah taa
Table 5-7 Diagnostic Port Read Operation AC Timing
Signal Symbol Parameter Min Max
AD[3:0] AD[3:0] RD_L AD RDY_L RD_L AS_L AD[7:0] AD[7:0] AS_L RDY_L
tas tah tar trd tryl tyr tya tds tdh taa tryh
Setup time to AS_L asserted Hold time from AS_L asserted Delay from AS_L asserted Delay from RD_L asserted to driven Delay from RD_L assertion Delay from RDY_L assertion Delay from RDY_L assertion Setup time to RDY_L assertion Minimu deassertion time Delay from RD_L deassertion
13ns 23ns 23ns 40ns 0ns 0ns 40ns 0ns 23ns 40ns
- - - 55ns infinite - - - 55ns - 55ns
Hold time from AS_L deassertion 40ns
Table 5-8 Diagnostic Port Write Operation Timing Diagram
tya tas AS_L taw WR_L RD_L twyl RDY_L tdh AD[7:0] ADDR DATA twyh tah tds twh taa
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Table 5-9 Diagnostic Port Write Operation AC Timing
Signal Symbol Parameter Min Max
AD[3:0] AD[3:0] AD[7:0] AD[7:0] WR_L RDY_L RDY_L WR_L AS_L AS_L
tas tah tds tdh twh twyl twyh taw taa tya
Setup time to AS_L asserted Hold time from AS_L asserted Setup time to WR_L asserted Hold time from RDY_L asserted Delay from WR_L assertion Delay from WR_L deassertion Delay from AS_L assertion Minimum deassertion time Delay from RDY_L deassertion
13ns 23ns 13ns 0ns 40ns 40ns 36ns 23ns 0ns
- - - - - 55ns 55ns - - -
Hold time from RDY_L assertion 0ns
5.3.5 JTAG Timing
Table 5-10 JTAG Signal AC TIming Specifications
Signal Symbol Parameter Min Max
TCK TCK TCK TDI, TMS TDI, TMS TDO TDO
Fftck Ttckl Ttckh Ttsu Tth Ttval Ttz
Frequency Time low Time high Setup to TCK Hold from TCK Valid from TCK Hi-Z from TCK
- 50ns 50ns 40ns 40ns - 5ns
10MHz - - - - 30ns 40ns
5.3.6 Asynchronous and Static Signals
Table 5-11 Asynchronous and Static Signals
Signal Note
GPIO[7:0] CTAP0[3:0], CTAP1[3:0], RESLO, RESHI BYPASSL, RESETTX, RESETRX, TSTSHFTLD, ECSEL, ETOGGLE, EXDNUP, TSTPHASE, LOOPBKEN TESTMODE[4:0]
Under software control LVDS control. Static. Asynchronous
Static
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Electrical Specifications
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6
Contact Information
6.1 Headquarters
StarGen Inc. 225 Cedar Hill St. Suite 22 Marlborough, Ma 01752
Voice: (508) 786-9950 Fax: (508) 786-9785
Web: www.StarGen.com Email: Info@ StarGen.com
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